30 lines
910 B
Verilog
30 lines
910 B
Verilog
// Simple test of the UART pins and clock, no CPU needed
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module top(input clk, output ser_tx, input ser_rx, output [13:0] led);
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//assign ser_tx = test_chars; // uncomment for a bunch of ASCII "U" characters
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assign ser_tx = ser_rx; // uncomment first for serial echo
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assign led = 'b11111111111110;
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wire serclk;
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reg test_chars;
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clkdiv clock_generator (clk, serclk);
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always @(posedge serclk) begin
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test_chars = !test_chars;
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end
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endmodule
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module clkdiv(input clock_in, output reg clock_out);
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reg[15:0] counter=16'd0;
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parameter DIVISOR = 16'd104; //set according to desired baudrate for test characters (e.g. 12,000,000 Hz / 115200 baud ~= clock divider 104)
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always @(posedge clock_in) begin
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counter <= counter + 16'd1;
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if(counter>=(DIVISOR-1))
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counter <= 16'd0;
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clock_out <= (counter<DIVISOR/2)?1'b1:1'b0;
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end
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endmodule |