Add UART test code

Makefile

@@ -0,0 +1,22 @@
+buildpath = build/
+filename = uart_test
+files = top.v
+pcf_file = io.pcf
+
+.PHONY: build prog prog_flash clean
+
+build:
+	#yosys -p "synth_ice40 -blif $(buildpath)$(filename).blif -top top" $(files)
+	#arachne-pnr -r -d 5k -P sg48 -p $(pcf_file) $(buildpath)$(filename).blif -o $(buildpath)$(filename).asc
+	yosys -p "synth_ice40 -json $(buildpath)$(filename).json -top top" $(files)
+	nextpnr-ice40 --up5k --json $(buildpath)$(filename).json --pcf $(pcf_file) --asc $(buildpath)$(filename).asc
+	icepack $(buildpath)$(filename).asc $(buildpath)$(filename).bin
+
+prog: build #for sram
+	iceprog -S $(buildpath)$(filename).bin
+
+prog_flash: build
+	iceprog $(buildpath)$(filename).bin
+
+clean:
+	rm -rf $(buildpath)/*

build/.gitignore

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+# ignore everything here
+*
+# let the gitignore stay
+!.gitignore

io.pcf

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+# 12 MHz clock
+set_io clk        35
+
+# RS232
+set_io ser_rx      26
+set_io ser_tx      27
+
+# SPI Flash
+set_io flash_clk  15
+set_io flash_csb  16
+set_io flash_io0  14
+set_io flash_io1  17
+#set_io flash_io2  12
+#set_io flash_io3  13
+
+# LEDs (PMOD 2)
+set_io led1       39
+set_io led2       40
+set_io led3       41
+set_io led4       23
+set_io led5       25
+
+# Onboard LEDs
+set_io ledr_n     11
+set_io ledg_n     37

top.v

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+// Simple test of the UART pins and clock, no CPU needed
+
+module top(input clk, output ser_tx, input ser_rx);
+    //assign ser_tx = test_chars; // uncomment for a bunch of ASCII "U" characters
+    assign ser_tx = ser_rx; // uncomment first for serial echo
+    
+    wire serclk;
+    reg test_chars;
+
+    clkdiv clock_generator (clk, serclk);
+
+    always @(posedge serclk) begin
+		test_chars = !test_chars;
+	end
+endmodule
+
+module clkdiv(input clock_in, output reg clock_out);
+    reg[15:0] counter=16'd0;
+    parameter DIVISOR = 16'd104; //set according to desired baudrate for test characters (e.g. 12,000,000 Hz / 115200 baud ~= clock divider 104)
+
+    always @(posedge clock_in) begin
+        counter <= counter + 16'd1;
+        if(counter>=(DIVISOR-1))
+            counter <= 16'd0;
+
+        clock_out <= (counter<DIVISOR/2)?1'b1:1'b0;
+    end
+endmodule