380 lines
5.5 KiB
ArmAsm
380 lines
5.5 KiB
ArmAsm
.text
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.globl add_mod_256
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.hidden add_mod_256
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.type add_mod_256,%function
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.align 5
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add_mod_256:
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ldp x8,x9,[x1]
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ldp x12,x13,[x2]
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ldp x10,x11,[x1,#16]
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adds x8,x8,x12
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ldp x14,x15,[x2,#16]
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adcs x9,x9,x13
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ldp x4,x5,[x3]
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adcs x10,x10,x14
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ldp x6,x7,[x3,#16]
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adcs x11,x11,x15
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adc x3,xzr,xzr
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subs x16,x8,x4
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sbcs x17,x9,x5
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sbcs x1,x10,x6
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sbcs x2,x11,x7
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sbcs xzr,x3,xzr
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csel x8,x8,x16,lo
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csel x9,x9,x17,lo
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csel x10,x10,x1,lo
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stp x8,x9,[x0]
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csel x11,x11,x2,lo
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stp x10,x11,[x0,#16]
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ret
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.size add_mod_256,.-add_mod_256
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.globl mul_by_3_mod_256
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.hidden mul_by_3_mod_256
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.type mul_by_3_mod_256,%function
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.align 5
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mul_by_3_mod_256:
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ldp x12,x13,[x1]
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ldp x14,x15,[x1,#16]
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adds x8,x12,x12
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ldp x4,x5,[x2]
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adcs x9,x13,x13
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ldp x6,x7,[x2,#16]
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adcs x10,x14,x14
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adcs x11,x15,x15
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adc x3,xzr,xzr
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subs x16,x8,x4
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sbcs x17,x9,x5
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sbcs x1,x10,x6
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sbcs x2,x11,x7
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sbcs xzr,x3,xzr
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csel x8,x8,x16,lo
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csel x9,x9,x17,lo
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csel x10,x10,x1,lo
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csel x11,x11,x2,lo
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adds x8,x8,x12
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adcs x9,x9,x13
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adcs x10,x10,x14
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adcs x11,x11,x15
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adc x3,xzr,xzr
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subs x16,x8,x4
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sbcs x17,x9,x5
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sbcs x1,x10,x6
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sbcs x2,x11,x7
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sbcs xzr,x3,xzr
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csel x8,x8,x16,lo
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csel x9,x9,x17,lo
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csel x10,x10,x1,lo
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stp x8,x9,[x0]
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csel x11,x11,x2,lo
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stp x10,x11,[x0,#16]
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ret
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.size mul_by_3_mod_256,.-mul_by_3_mod_256
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.globl lshift_mod_256
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.hidden lshift_mod_256
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.type lshift_mod_256,%function
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.align 5
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lshift_mod_256:
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ldp x8,x9,[x1]
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ldp x10,x11,[x1,#16]
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ldp x4,x5,[x3]
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ldp x6,x7,[x3,#16]
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.Loop_lshift_mod_256:
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adds x8,x8,x8
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sub x2,x2,#1
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adcs x9,x9,x9
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adcs x10,x10,x10
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adcs x11,x11,x11
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adc x3,xzr,xzr
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subs x12,x8,x4
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sbcs x13,x9,x5
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sbcs x14,x10,x6
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sbcs x15,x11,x7
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sbcs xzr,x3,xzr
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csel x8,x8,x12,lo
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csel x9,x9,x13,lo
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csel x10,x10,x14,lo
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csel x11,x11,x15,lo
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cbnz x2,.Loop_lshift_mod_256
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stp x8,x9,[x0]
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stp x10,x11,[x0,#16]
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ret
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.size lshift_mod_256,.-lshift_mod_256
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.globl rshift_mod_256
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.hidden rshift_mod_256
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.type rshift_mod_256,%function
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.align 5
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rshift_mod_256:
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ldp x8,x9,[x1]
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ldp x10,x11,[x1,#16]
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ldp x4,x5,[x3]
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ldp x6,x7,[x3,#16]
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.Loop_rshift:
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adds x12,x8,x4
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sub x2,x2,#1
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adcs x13,x9,x5
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adcs x14,x10,x6
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adcs x15,x11,x7
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adc x3,xzr,xzr
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tst x8,#1
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csel x12,x12,x8,ne
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csel x13,x13,x9,ne
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csel x14,x14,x10,ne
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csel x15,x15,x11,ne
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csel x3,x3,xzr,ne
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extr x8,x13,x12,#1
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extr x9,x14,x13,#1
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extr x10,x15,x14,#1
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extr x11,x3,x15,#1
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cbnz x2,.Loop_rshift
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stp x8,x9,[x0]
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stp x10,x11,[x0,#16]
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ret
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.size rshift_mod_256,.-rshift_mod_256
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.globl cneg_mod_256
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.hidden cneg_mod_256
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.type cneg_mod_256,%function
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.align 5
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cneg_mod_256:
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ldp x8,x9,[x1]
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ldp x4,x5,[x3]
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ldp x10,x11,[x1,#16]
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subs x12,x4,x8
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ldp x6,x7,[x3,#16]
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orr x4,x8,x9
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sbcs x13,x5,x9
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orr x5,x10,x11
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sbcs x14,x6,x10
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orr x3,x4,x5
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sbc x15,x7,x11
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cmp x3,#0
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csetm x3,ne
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ands x2,x2,x3
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csel x8,x8,x12,eq
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csel x9,x9,x13,eq
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csel x10,x10,x14,eq
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stp x8,x9,[x0]
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csel x11,x11,x15,eq
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stp x10,x11,[x0,#16]
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ret
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.size cneg_mod_256,.-cneg_mod_256
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.globl sub_mod_256
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.hidden sub_mod_256
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.type sub_mod_256,%function
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.align 5
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sub_mod_256:
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ldp x8,x9,[x1]
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ldp x12,x13,[x2]
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ldp x10,x11,[x1,#16]
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subs x8,x8,x12
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ldp x14,x15,[x2,#16]
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sbcs x9,x9,x13
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ldp x4,x5,[x3]
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sbcs x10,x10,x14
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ldp x6,x7,[x3,#16]
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sbcs x11,x11,x15
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sbc x3,xzr,xzr
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and x4,x4,x3
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and x5,x5,x3
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adds x8,x8,x4
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and x6,x6,x3
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adcs x9,x9,x5
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and x7,x7,x3
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adcs x10,x10,x6
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stp x8,x9,[x0]
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adc x11,x11,x7
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stp x10,x11,[x0,#16]
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ret
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.size sub_mod_256,.-sub_mod_256
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.globl check_mod_256
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.hidden check_mod_256
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.type check_mod_256,%function
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.align 5
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check_mod_256:
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ldp x8,x9,[x0]
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ldp x10,x11,[x0,#16]
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ldp x4,x5,[x1]
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ldp x6,x7,[x1,#16]
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x9,x9
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rev x10,x10
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rev x11,x11
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#endif
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subs xzr,x8,x4
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sbcs xzr,x9,x5
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orr x8,x8,x9
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sbcs xzr,x10,x6
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orr x8,x8,x10
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sbcs xzr,x11,x7
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orr x8,x8,x11
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sbc x1,xzr,xzr
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cmp x8,#0
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mov x0,#1
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csel x0,x0,xzr,ne
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and x0,x0,x1
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ret
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.size check_mod_256,.-check_mod_256
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.globl add_n_check_mod_256
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.hidden add_n_check_mod_256
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.type add_n_check_mod_256,%function
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.align 5
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add_n_check_mod_256:
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ldp x8,x9,[x1]
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ldp x12,x13,[x2]
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ldp x10,x11,[x1,#16]
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ldp x14,x15,[x2,#16]
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x12,x12
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rev x9,x9
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rev x13,x13
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rev x10,x10
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rev x14,x14
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rev x11,x11
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rev x15,x15
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#endif
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adds x8,x8,x12
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ldp x4,x5,[x3]
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adcs x9,x9,x13
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ldp x6,x7,[x3,#16]
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adcs x10,x10,x14
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adcs x11,x11,x15
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adc x3,xzr,xzr
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subs x16,x8,x4
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sbcs x17,x9,x5
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sbcs x1,x10,x6
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sbcs x2,x11,x7
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sbcs xzr,x3,xzr
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csel x8,x8,x16,lo
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csel x9,x9,x17,lo
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csel x10,x10,x1,lo
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csel x11,x11,x2,lo
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orr x16, x8, x9
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orr x17, x10, x11
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orr x16, x16, x17
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x9,x9
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rev x10,x10
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rev x11,x11
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#endif
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stp x8,x9,[x0]
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stp x10,x11,[x0,#16]
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mov x17, #1
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cmp x16, #0
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csel x0, x17, xzr, ne
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ret
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.size add_n_check_mod_256,.-add_n_check_mod_256
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.globl sub_n_check_mod_256
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.hidden sub_n_check_mod_256
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.type sub_n_check_mod_256,%function
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.align 5
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sub_n_check_mod_256:
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ldp x8,x9,[x1]
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ldp x12,x13,[x2]
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ldp x10,x11,[x1,#16]
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ldp x14,x15,[x2,#16]
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x12,x12
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rev x9,x9
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rev x13,x13
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rev x10,x10
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rev x14,x14
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rev x11,x11
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rev x15,x15
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#endif
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subs x8,x8,x12
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sbcs x9,x9,x13
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ldp x4,x5,[x3]
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sbcs x10,x10,x14
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ldp x6,x7,[x3,#16]
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sbcs x11,x11,x15
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sbc x3,xzr,xzr
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and x4,x4,x3
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and x5,x5,x3
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adds x8,x8,x4
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and x6,x6,x3
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adcs x9,x9,x5
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and x7,x7,x3
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adcs x10,x10,x6
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adc x11,x11,x7
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orr x16, x8, x9
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orr x17, x10, x11
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orr x16, x16, x17
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#ifdef __AARCH64EB__
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rev x8,x8
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rev x9,x9
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rev x10,x10
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rev x11,x11
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#endif
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stp x8,x9,[x0]
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stp x10,x11,[x0,#16]
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mov x17, #1
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cmp x16, #0
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csel x0, x17, xzr, ne
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ret
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.size sub_n_check_mod_256,.-sub_n_check_mod_256
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