From bac8900e3d429e60ba2c74b12439a1890c3eee55 Mon Sep 17 00:00:00 2001
From: John Doe <johndoe@example.com>
Date: Tue, 3 May 2022 13:37:22 -0400
Subject: [PATCH] Add Nexus support

---
 Makefile | 20 +++++++++++----
 io.pdc   | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 top.v    |  4 ++-
 3 files changed, 95 insertions(+), 6 deletions(-)
 create mode 100644 io.pdc

diff --git a/Makefile b/Makefile
index e064253..3e853df 100644
--- a/Makefile
+++ b/Makefile
@@ -2,21 +2,31 @@ buildpath = build/
 filename = uart_test
 files = top.v
 pcf_file = io.pcf
+pdc_file = io.pdc
 
 .PHONY: build prog prog_flash clean
 
-build:
-	#yosys -p "synth_ice40 -blif $(buildpath)$(filename).blif -top top" $(files)
-	#arachne-pnr -r -d 5k -P sg48 -p $(pcf_file) $(buildpath)$(filename).blif -o $(buildpath)$(filename).asc
+build_ice40:
 	yosys -p "synth_ice40 -json $(buildpath)$(filename).json -top top" $(files)
 	nextpnr-ice40 --up5k --json $(buildpath)$(filename).json --pcf $(pcf_file) --asc $(buildpath)$(filename).asc
 	icepack $(buildpath)$(filename).asc $(buildpath)$(filename).bin
 
-prog: build #for sram
+prog_ice40: build #for sram
 	iceprog -S $(buildpath)$(filename).bin
 
-prog_flash: build
+prog_flash_ice40: build
 	iceprog $(buildpath)$(filename).bin
 
+build_nx: 
+	yosys -p "synth_nexus -json $(buildpath)$(filename).json -top top" $(files)
+	nextpnr-nexus --device LIFCL-40-9BG400 --pdc $(pdc_file) --json $(buildpath)$(filename).json --fasm $(buildpath)$(filename).fasm
+	prjoxide pack $(buildpath)$(filename).fasm $(buildpath)$(filename).bit
+
+prog_nx:  #for sram
+	ecpprog -S $(buildpath)$(filename).bit
+
+prog_flash_nx: 
+	ecpprog $(buildpath)$(filename).bit
+
 clean:
 	rm -rf $(buildpath)/*
\ No newline at end of file
diff --git a/io.pdc b/io.pdc
new file mode 100644
index 0000000..a36fee8
--- /dev/null
+++ b/io.pdc
@@ -0,0 +1,77 @@
+# 12MHz Clock:
+ldc_set_location -site {L13} [get_ports {clk}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {clk}]
+
+# RS232:
+ldc_set_location -site {D6} [get_ports {ser_rx}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {ser_rx}]
+
+ldc_set_location -site {D10} [get_ports {ser_tx}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {ser_tx}]
+
+# SPI Flash:
+ldc_set_location -site {E12} [get_ports {flash_clk}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {flash_clk}]
+
+ldc_set_location -site {E13} [get_ports {flash_csb}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {flash_csb}]
+
+ldc_set_location -site {D13} [get_ports {flash_io0}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {flash_io0}]
+
+ldc_set_location -site {D15} [get_ports {flash_io1}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {flash_io1}]
+
+# LEDs:
+ldc_set_location -site {E17} [get_ports {led1}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led1}]
+
+ldc_set_location -site {F13} [get_ports {led2}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {l3d2}]
+
+ldc_set_location -site {G13} [get_ports {led3}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led3}]
+
+ldc_set_location -site {F14} [get_ports {led4}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led4}]
+
+ldc_set_location -site {L16} [get_ports {led5}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led5}]
+
+ldc_set_location -site {W20} [get_ports {ledr_n}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {ledr_n}]
+
+ldc_set_location -site {V20} [get_ports {ledg_n}]
+ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {ledg_n}]
+
+# LEDs:
+#ldc_set_location -site {E17} [get_ports {led[0]}]
+#ldc_set_location -site {F13} [get_ports {led[1]}]
+#ldc_set_location -site {G13} [get_ports {led[2]}]
+#ldc_set_location -site {F14} [get_ports {led[3]}]
+#ldc_set_location -site {L16} [get_ports {led[4]}]
+#ldc_set_location -site {L15} [get_ports {led[5]}]
+#ldc_set_location -site {L20} [get_ports {led[6]}]
+#ldc_set_location -site {L19} [get_ports {led[7]}]
+#ldc_set_location -site {R17} [get_ports {led[8]}]
+#ldc_set_location -site {R18} [get_ports {led[9]}]
+#ldc_set_location -site {U20} [get_ports {led[10]}]
+#ldc_set_location -site {T20} [get_ports {led[11]}]
+#ldc_set_location -site {W20} [get_ports {led[12]}]
+#ldc_set_location -site {V20} [get_ports {led[13]}]
+#ldc_set_location -site {G19} [get_ports gsrn]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[0]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[1]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[2]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[3]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[4]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[5]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[6]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[7]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[8]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[9]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[10]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[11]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[12]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports {led[13]}]
+#ldc_set_port -iobuf {IO_TYPE=LVCMOS33} [get_ports gsrn]
\ No newline at end of file
diff --git a/top.v b/top.v
index ffbd7c9..d2009eb 100644
--- a/top.v
+++ b/top.v
@@ -1,8 +1,10 @@
 // Simple test of the UART pins and clock, no CPU needed
 
-module top(input clk, output ser_tx, input ser_rx);
+module top(input clk, output ser_tx, input ser_rx, output [13:0] led);
     //assign ser_tx = test_chars; // uncomment for a bunch of ASCII "U" characters
     assign ser_tx = ser_rx; // uncomment first for serial echo
+
+    assign led = 'b11111111111110;
     
     wire serclk;
     reg test_chars;