EESchema Schematic File Version 4 EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 Sheet 4 5 Title "" Date "" Rev "" Comp "" Comment1 "" Comment2 "" Comment3 "" Comment4 "" $EndDescr Wire Wire Line 2900 6550 2900 6650 $Comp L power:GND #PWR? U 1 1 62B4885D P 2400 7450 AR Path="/62B4885D" Ref="#PWR?" Part="1" AR Path="/61CBBC03/62B4885D" Ref="#PWR?" Part="1" AR Path="/629A862A/62B4885D" Ref="#PWR0136" Part="1" F 0 "#PWR0136" H 2400 7200 50 0001 C CNN F 1 "GND" H 2405 7277 50 0000 C CNN F 2 "" H 2400 7450 50 0001 C CNN F 3 "" H 2400 7450 50 0001 C CNN 1 2400 7450 1 0 0 -1 $EndComp Wire Wire Line 2400 7450 2400 7350 Wire Wire Line 2600 7000 2500 7000 Wire Wire Line 2500 7000 2500 6650 Wire Wire Line 2500 6650 2900 6650 Connection ~ 2900 6650 Wire Wire Line 2900 6650 2900 6700 $Comp L Device:C C? U 1 1 62B48869 P 2200 7000 AR Path="/62B48869" Ref="C?" Part="1" AR Path="/61CBBC03/62B48869" Ref="C?" Part="1" AR Path="/629A862A/62B48869" Ref="C31" Part="1" F 0 "C31" H 2315 7046 50 0000 L CNN F 1 "0.1uF" H 2315 6955 50 0000 L CNN F 2 "Capacitor_SMD:C_0603_1608Metric" H 2238 6850 50 0001 C CNN F 3 "~" H 2200 7000 50 0001 C CNN 1 2200 7000 1 0 0 -1 $EndComp Wire Wire Line 2500 6650 2200 6650 Wire Wire Line 2200 6650 2200 6850 Connection ~ 2500 6650 Wire Wire Line 2200 7150 2200 7350 Wire Wire Line 2200 7350 2400 7350 Text GLabel 4300 7100 2 50 Input ~ 0 CLKB Text Notes 3250 6500 0 118 ~ 0 System Clock Text GLabel 4300 6900 2 50 Input ~ 0 CLKA $Comp L ETXO_Osc:ETXO-4Pin U? U 1 1 62B48877 P 2900 7000 AR Path="/62B48877" Ref="U?" Part="1" AR Path="/61CBBC03/62B48877" Ref="U?" Part="1" AR Path="/629A862A/62B48877" Ref="U9" Part="1" F 0 "U9" H 2700 7250 50 0000 L CNN F 1 "ETXO-4Pin" H 2950 7250 50 0000 L CNN F 2 "ECP5_BOARD:OSC_ECS-TXO-25CSMV-320-DY-TR" H 2900 7000 50 0001 C CNN F 3 "" H 2900 7000 50 0001 C CNN 1 2900 7000 1 0 0 -1 $EndComp Wire Wire Line 2900 7300 2900 7350 Wire Wire Line 2900 7350 2400 7350 Connection ~ 2400 7350 Text Notes 3100 7600 0 50 ~ 0 Connect both jumpers to use onboard\nXO instead of external clock $Comp L Device:Jumper JP? U 1 1 62B4888D P 3800 6900 AR Path="/61CBBC03/62B4888D" Ref="JP?" Part="1" AR Path="/629A862A/62B4888D" Ref="JP2" Part="1" F 0 "JP2" V 3750 7150 50 0000 R CNN F 1 "Jumper" V 3900 7250 50 0000 R CNN F 2 "Connector_PinHeader_1.27mm:PinHeader_1x02_P1.27mm_Vertical" H 3800 6900 50 0001 C CNN F 3 "~" H 3800 6900 50 0001 C CNN 1 3800 6900 -1 0 0 -1 $EndComp $Comp L Device:Jumper JP? U 1 1 62B48896 P 3800 7100 AR Path="/61CBBC03/62B48896" Ref="JP?" Part="1" AR Path="/629A862A/62B48896" Ref="JP3" Part="1" F 0 "JP3" V 3750 7350 50 0000 R CNN F 1 "Jumper" V 3900 7450 50 0000 R CNN F 2 "Connector_PinHeader_1.27mm:PinHeader_1x02_P1.27mm_Vertical" H 3800 7100 50 0001 C CNN F 3 "~" H 3800 7100 50 0001 C CNN 1 3800 7100 -1 0 0 1 $EndComp $Comp L power:VBUS #PWR0138 U 1 1 62B4C07B P 2900 6550 F 0 "#PWR0138" H 2900 6400 50 0001 C CNN F 1 "VBUS" H 2915 6723 50 0000 C CNN F 2 "" H 2900 6550 50 0001 C CNN F 3 "" H 2900 6550 50 0001 C CNN 1 2900 6550 1 0 0 -1 $EndComp $Comp L power:VBUS #PWR0139 U 1 1 62B7CF62 P 5300 6750 F 0 "#PWR0139" H 5300 6600 50 0001 C CNN F 1 "VBUS" H 5315 6923 50 0000 C CNN F 2 "" H 5300 6750 50 0001 C CNN F 3 "" H 5300 6750 50 0001 C CNN 1 5300 6750 1 0 0 -1 $EndComp $Comp L power:+1V8 #PWR0140 U 1 1 62B7E6D5 P 5900 6750 F 0 "#PWR0140" H 5900 6600 50 0001 C CNN F 1 "+1V8" H 5915 6923 50 0000 C CNN F 2 "" H 5900 6750 50 0001 C CNN F 3 "" H 5900 6750 50 0001 C CNN 1 5900 6750 1 0 0 -1 $EndComp $Comp L Device:Jumper JP? U 1 1 62B7F21D P 5600 7000 AR Path="/61CBBC03/62B7F21D" Ref="JP?" Part="1" AR Path="/629A862A/62B7F21D" Ref="JP1" Part="1" F 0 "JP1" V 5550 7250 50 0000 R CNN F 1 "Jumper" V 5700 7350 50 0000 R CNN F 2 "Connector_PinHeader_1.27mm:PinHeader_1x02_P1.27mm_Vertical" H 5600 7000 50 0001 C CNN F 3 "~" H 5600 7000 50 0001 C CNN 1 5600 7000 1 0 0 -1 $EndComp Wire Wire Line 5900 6750 5900 7000 Wire Wire Line 5300 7000 5300 6750 Text Notes 4850 7450 0 50 ~ 0 Connect jumper to use onboard 1.8V\nas VBUS for I/O and clock (incl. onboard osc.) Text GLabel 1150 7050 0 50 Input ~ 0 ID0 Text GLabel 1150 7150 0 50 Input ~ 0 ID1 $Comp L Device:R_US R? U 1 1 62BBA733 P 1250 6800 AR Path="/62BBA733" Ref="R?" Part="1" AR Path="/61CBBC03/62BBA733" Ref="R?" Part="1" AR Path="/629A862A/62BBA733" Ref="R13" Part="1" F 0 "R13" H 1182 6754 50 0000 R CNN F 1 "4.7k" H 1182 6845 50 0000 R CNN F 2 "Resistor_SMD:R_0603_1608Metric" V 1290 6790 50 0001 C CNN F 3 "~" H 1250 6800 50 0001 C CNN 1 1250 6800 1 0 0 1 $EndComp $Comp L Device:R_US R? U 1 1 62BBA73F P 1450 6800 AR Path="/62BBA73F" Ref="R?" Part="1" AR Path="/61CBBC03/62BBA73F" Ref="R?" Part="1" AR Path="/629A862A/62BBA73F" Ref="R14" Part="1" F 0 "R14" H 1518 6846 50 0000 L CNN F 1 "4.7k" H 1518 6755 50 0000 L CNN F 2 "Resistor_SMD:R_0603_1608Metric" V 1490 6790 50 0001 C CNN F 3 "~" H 1450 6800 50 0001 C CNN 1 1450 6800 1 0 0 -1 $EndComp Wire Wire Line 1250 6950 1250 7050 Wire Wire Line 1250 7050 1150 7050 Wire Wire Line 1450 6950 1450 7150 Wire Wire Line 1450 7150 1150 7150 Wire Wire Line 1250 6650 1250 6600 Wire Wire Line 1250 6600 1350 6600 Wire Wire Line 1350 6600 1350 6550 Wire Wire Line 1350 6600 1450 6600 Wire Wire Line 1450 6600 1450 6650 Connection ~ 1350 6600 Text Notes 700 7350 0 118 ~ 0 Core ID pullup Text Notes 950 7550 0 50 ~ 0 Defaults core ID\nto 3 (standalone) $Comp L power:VBUS #PWR0141 U 1 1 62BBE019 P 1350 6550 F 0 "#PWR0141" H 1350 6400 50 0001 C CNN F 1 "VBUS" H 1365 6723 50 0000 C CNN F 2 "" H 1350 6550 50 0001 C CNN F 3 "" H 1350 6550 50 0001 C CNN 1 1350 6550 1 0 0 -1 $EndComp Text GLabel 800 2850 0 50 Input ~ 0 UP_L Text GLabel 800 2950 0 50 Input ~ 0 UP_R Text GLabel 800 2750 0 50 Input ~ 0 ID1 Text GLabel 800 2650 0 50 Input ~ 0 ID0 Text GLabel 800 3050 0 50 Input ~ 0 SC_L Text GLabel 800 3150 0 50 Input ~ 0 SC_R $Comp L power:VBUS #PWR0142 U 1 1 62CA27EF P 2300 1250 F 0 "#PWR0142" H 2300 1100 50 0001 C CNN F 1 "VBUS" H 2315 1423 50 0000 C CNN F 2 "" H 2300 1250 50 0001 C CNN F 3 "" H 2300 1250 50 0001 C CNN 1 2300 1250 1 0 0 -1 $EndComp Wire Wire Line 2300 1250 2300 1350 Text Notes 4700 7250 0 118 ~ 0 Optional Onboard VBUS Text Notes 7150 6900 0 118 ~ 0 I/O and Clock Wire Wire Line 3200 7000 3400 7000 Wire Wire Line 3400 7000 3400 6900 Wire Wire Line 3400 6900 3500 6900 Wire Wire Line 3400 7000 3400 7100 Wire Wire Line 3400 7100 3500 7100 Connection ~ 3400 7000 Wire Wire Line 4300 6900 4100 6900 Wire Wire Line 4100 7100 4300 7100 $Comp L power:VBUS #PWR01 U 1 1 61760C08 P 4550 1150 F 0 "#PWR01" H 4550 1000 50 0001 C CNN F 1 "VBUS" H 4565 1323 50 0000 C CNN F 2 "" H 4550 1150 50 0001 C CNN F 3 "" H 4550 1150 50 0001 C CNN 1 4550 1150 1 0 0 -1 $EndComp Wire Wire Line 4550 1150 4550 1250 $Comp L power:VBUS #PWR02 U 1 1 617631B1 P 6700 1250 F 0 "#PWR02" H 6700 1100 50 0001 C CNN F 1 "VBUS" H 6715 1423 50 0000 C CNN F 2 "" H 6700 1250 50 0001 C CNN F 3 "" H 6700 1250 50 0001 C CNN 1 6700 1250 1 0 0 -1 $EndComp Wire Wire Line 6700 1250 6700 1350 $Comp L power:VBUS #PWR03 U 1 1 617657B4 P 8800 1250 F 0 "#PWR03" H 8800 1100 50 0001 C CNN F 1 "VBUS" H 8815 1423 50 0000 C CNN F 2 "" H 8800 1250 50 0001 C CNN F 3 "" H 8800 1250 50 0001 C CNN 1 8800 1250 1 0 0 -1 $EndComp Wire Wire Line 8800 1250 8800 1350 $Comp L power:VBUS #PWR04 U 1 1 61775788 P 11000 1350 F 0 "#PWR04" H 11000 1200 50 0001 C CNN F 1 "VBUS" H 11015 1523 50 0000 C CNN F 2 "" H 11000 1350 50 0001 C CNN F 3 "" H 11000 1350 50 0001 C CNN 1 11000 1350 1 0 0 -1 $EndComp Wire Wire Line 11000 1350 11000 1450 Text Notes 9550 5800 0 118 ~ 0 GPIO Bank 5 Text Notes 7500 5800 0 118 ~ 0 GPIO Bank 4 Text Notes 1100 5800 0 118 ~ 0 GPIO Bank 1 Text Notes 3150 5800 0 118 ~ 0 GPIO Bank 2 Text Notes 5350 5800 0 118 ~ 0 GPIO Bank 3 $Comp L Lattice_ECP5_FPGA:ECP5U_85_CABGA381 U? U 7 1 615DFD6A P 9100 2350 AR Path="/6255F87B/615DFD6A" Ref="U?" Part="1" AR Path="/629A862A/615DFD6A" Ref="U1" Part="7" F 0 "U1" H 9350 2950 60 0000 L CNN F 1 "ECP5U_85_CABGA381" H 9350 2850 60 0000 L CNN F 2 "Package_BGA:Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD" H 9250 2400 60 0001 R CNN F 3 "" H 9250 2200 60 0001 R CNN F 4 "ECP5U_85" H 9250 2300 60 0001 R CNN "manf#" 7 9100 2350 1 0 0 -1 $EndComp $Comp L Lattice_ECP5_FPGA:ECP5U_85_CABGA381 U? U 6 1 615D9C13 P 7000 2250 AR Path="/6255F87B/615D9C13" Ref="U?" Part="1" AR Path="/629A862A/615D9C13" Ref="U1" Part="6" F 0 "U1" H 7250 2850 60 0000 L CNN F 1 "ECP5U_85_CABGA381" H 7250 2750 60 0000 L CNN F 2 "Package_BGA:Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD" H 7150 2300 60 0001 R CNN F 3 "" H 7150 2100 60 0001 R CNN F 4 "ECP5U_85" H 7150 2200 60 0001 R CNN "manf#" 6 7000 2250 1 0 0 -1 $EndComp $Comp L Lattice_ECP5_FPGA:ECP5U_85_CABGA381 U? U 4 1 615CE8F7 P 2650 2150 AR Path="/6255F87B/615CE8F7" Ref="U?" Part="1" AR Path="/629A862A/615CE8F7" Ref="U1" Part="4" F 0 "U1" H 2900 2750 60 0000 L CNN F 1 "ECP5U_85_CABGA381" H 2900 2650 60 0000 L CNN F 2 "Package_BGA:Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD" H 2800 2200 60 0001 R CNN F 3 "" H 2800 2000 60 0001 R CNN F 4 "ECP5U_85" H 2800 2100 60 0001 R CNN "manf#" 4 2650 2150 1 0 0 -1 $EndComp $Comp L Lattice_ECP5_FPGA:ECP5U_85_CABGA381 U? U 3 1 615C5AA3 P 800 2250 AR Path="/6255F87B/615C5AA3" Ref="U?" Part="1" AR Path="/629A862A/615C5AA3" Ref="U1" Part="3" F 0 "U1" H 1050 2850 60 0000 L CNN F 1 "ECP5U_85_CABGA381" H 1050 2750 60 0000 L CNN F 2 "Package_BGA:Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD" H 950 2300 60 0001 R CNN F 3 "" H 950 2100 60 0001 R CNN F 4 "ECP5U_85" H 950 2200 60 0001 R CNN "manf#" 3 800 2250 1 0 0 -1 $EndComp Text GLabel 800 3450 0 50 Input ~ 0 UP Text GLabel 800 3550 0 50 Input ~ 0 SC Text GLabel 800 3650 0 50 Input ~ 0 CARD_RX Text GLabel 800 3750 0 50 Input ~ 0 CARD_TX Text GLabel 800 3850 0 50 Input ~ 0 A15 Text GLabel 800 3950 0 50 Input ~ 0 B15 Text GLabel 800 4050 0 50 Input ~ 0 C15 Text GLabel 800 4150 0 50 Input ~ 0 D15 Text GLabel 800 4250 0 50 Input ~ 0 E15 Text GLabel 800 4350 0 50 Input ~ 0 A16 Text GLabel 800 4450 0 50 Input ~ 0 B16 Text GLabel 800 4550 0 50 Input ~ 0 C16 Text GLabel 800 4650 0 50 Input ~ 0 D16 Text GLabel 800 4750 0 50 Input ~ 0 B17 Text GLabel 800 4850 0 50 Input ~ 0 C17 Text GLabel 800 4950 0 50 Input ~ 0 A17 Text GLabel 800 5050 0 50 Input ~ 0 B18 Text GLabel 800 5150 0 50 Input ~ 0 A18 Text GLabel 800 5250 0 50 Input ~ 0 B19 Text GLabel 800 5350 0 50 Input ~ 0 A19 Text GLabel 800 5450 0 50 Input ~ 0 B20 Text GLabel 2650 2150 0 50 Input ~ 0 C18 Text GLabel 2650 2250 0 50 Input ~ 0 D17 Text GLabel 2650 2350 0 50 Input ~ 0 E16 Text GLabel 2650 2450 0 50 Input ~ 0 F16 Text GLabel 2650 2550 0 50 Input ~ 0 D18 Text GLabel 2650 2650 0 50 Input ~ 0 E17 Text GLabel 2650 2750 0 50 Input ~ 0 E18 Text GLabel 2650 2850 0 50 Input ~ 0 F18 Text GLabel 2650 2950 0 50 Input ~ 0 F17 Text GLabel 2650 3050 0 50 Input ~ 0 G18 Text GLabel 2650 3150 0 50 Input ~ 0 G16 Text GLabel 2650 3250 0 50 Input ~ 0 H16 Text GLabel 2650 3350 0 50 Input ~ 0 H18 Text GLabel 2650 3450 0 50 Input ~ 0 H17 Text GLabel 2650 3550 0 50 Input ~ 0 J17 Text GLabel 2650 3650 0 50 Input ~ 0 J16 Text GLabel 2650 3750 0 50 Input ~ 0 K16 Text GLabel 2650 3850 0 50 Input ~ 0 K17 Text GLabel 2650 3950 0 50 Input ~ 0 C20 Text GLabel 2650 4050 0 50 Input ~ 0 D19 Text GLabel 2650 4150 0 50 Input ~ 0 D20 Text GLabel 2650 4250 0 50 Input ~ 0 E19 Text GLabel 2650 4350 0 50 Input ~ 0 E20 Text GLabel 2650 4450 0 50 Input ~ 0 F19 Text GLabel 2650 4550 0 50 Input ~ 0 F20 Text GLabel 2650 4650 0 50 Input ~ 0 G20 Text GLabel 2650 4750 0 50 Input ~ 0 G19 Text GLabel 2650 4850 0 50 Input ~ 0 H20 Text GLabel 2650 4950 0 50 Input ~ 0 J18 Text GLabel 2650 5050 0 50 Input ~ 0 K18 Text GLabel 2650 5150 0 50 Input ~ 0 J19 Text GLabel 2650 5250 0 50 Input ~ 0 K19 Text GLabel 2650 5350 0 50 Input ~ 0 J20 Text GLabel 2650 5450 0 50 Input ~ 0 K20 Text GLabel 4900 2250 0 50 Input ~ 0 L20 Text GLabel 4900 2350 0 50 Input ~ 0 M20 Text GLabel 4900 2450 0 50 Input ~ 0 L19 Text GLabel 4900 2550 0 50 Input ~ 0 M19 Text GLabel 4900 2650 0 50 Input ~ 0 L16 Text GLabel 4900 2750 0 50 Input ~ 0 L17 Text GLabel 4900 2850 0 50 Input ~ 0 L18 Text GLabel 4900 2950 0 50 Input ~ 0 M18 Text GLabel 4900 3050 0 50 Input ~ 0 N16 Text GLabel 4900 3150 0 50 Input ~ 0 M17 Text GLabel 4900 3250 0 50 Input ~ 0 N18 Text GLabel 4900 3350 0 50 Input ~ 0 P17 Text GLabel 4900 3450 0 50 Input ~ 0 N17 Text GLabel 4900 3550 0 50 Input ~ 0 P16 Text GLabel 4900 3650 0 50 Input ~ 0 R16 Text GLabel 4900 3750 0 50 Input ~ 0 R17 Text GLabel 4900 3850 0 50 Input ~ 0 T16 Text GLabel 4900 3950 0 50 Input ~ 0 N19 Text GLabel 4900 4050 0 50 Input ~ 0 N20 Text GLabel 4900 4150 0 50 Input ~ 0 P19 Text GLabel 4900 4250 0 50 Input ~ 0 P18 Text GLabel 4900 4350 0 50 Input ~ 0 P20 Text GLabel 4900 4450 0 50 Input ~ 0 R20 Text GLabel 4900 4550 0 50 Input ~ 0 T20 Text GLabel 4900 4650 0 50 Input ~ 0 U20 Text GLabel 4900 4750 0 50 Input ~ 0 T19 Text GLabel 4900 4850 0 50 Input ~ 0 R18 Text GLabel 4900 4950 0 50 Input ~ 0 U19 Text GLabel 4900 5050 0 50 Input ~ 0 T18 Text GLabel 4900 5150 0 50 Input ~ 0 U18 Text GLabel 4900 5250 0 50 Input ~ 0 U17 Text GLabel 4900 5350 0 50 Input ~ 0 U16 Text GLabel 4900 5450 0 50 Input ~ 0 T17 Text GLabel 7000 2250 0 50 Input ~ 0 G2 Text GLabel 9100 2350 0 50 Input ~ 0 A4 Text GLabel 7000 2350 0 50 Input ~ 0 F1 Text GLabel 7000 2450 0 50 Input ~ 0 H2 Text GLabel 7000 2550 0 50 Input ~ 0 G1 Text GLabel 7000 2650 0 50 Input ~ 0 J4 Text GLabel 7000 2750 0 50 Input ~ 0 J5 Text GLabel 7000 2850 0 50 Input ~ 0 J3 Text GLabel 7000 2950 0 50 Input ~ 0 K3 Text GLabel 7000 3050 0 50 Input ~ 0 K2 Text GLabel 7000 3150 0 50 Input ~ 0 J1 Text GLabel 7000 3250 0 50 Input ~ 0 H1 Text GLabel 7000 3350 0 50 Input ~ 0 K1 Text GLabel 7000 3450 0 50 Input ~ 0 K4 Text GLabel 7000 3550 0 50 Input ~ 0 PRSNT_IN Text GLabel 7000 3650 0 50 Input ~ 0 L4 Text GLabel 7000 3750 0 50 Input ~ 0 L5 Text GLabel 7000 3850 0 50 Input ~ 0 M5 Text GLabel 7000 3950 0 50 Input ~ 0 M4 Text GLabel 7000 4050 0 50 Input ~ 0 N5 Text GLabel 7000 4150 0 50 Input ~ 0 N4 Text GLabel 7000 4250 0 50 Input ~ 0 P5 Text GLabel 7000 4350 0 50 Input ~ 0 N3 Text GLabel 7000 4450 0 50 Input ~ 0 M3 Text GLabel 7000 4550 0 50 Input ~ 0 L3 Text GLabel 7000 4650 0 50 Input ~ 0 L2 Text GLabel 7000 4750 0 50 Input ~ 0 N2 Text GLabel 7000 4850 0 50 Input ~ 0 M1 Text GLabel 7000 4950 0 50 Input ~ 0 L1 Text GLabel 7000 5050 0 50 Input ~ 0 N1 Text GLabel 7000 5150 0 50 Input ~ 0 P1 Text GLabel 7000 5250 0 50 Input ~ 0 P2 Text GLabel 7000 5350 0 50 Input ~ 0 P3 Text GLabel 7000 5450 0 50 Input ~ 0 P4 Text GLabel 9100 2450 0 50 Input ~ 0 A5 Text GLabel 9100 2550 0 50 Input ~ 0 B5 Text GLabel 9100 2650 0 50 Input ~ 0 C5 Text GLabel 9100 2750 0 50 Input ~ 0 C4 Text GLabel 9100 2850 0 50 Input ~ 0 B4 Text GLabel 9100 2950 0 50 Input ~ 0 A3 Text GLabel 9100 3050 0 50 Input ~ 0 B3 Text GLabel 9100 3150 0 50 Input ~ 0 E4 Text GLabel 9100 3250 0 50 Input ~ 0 D5 Text GLabel 9100 3350 0 50 Input ~ 0 C3 Text GLabel 9100 3450 0 50 Input ~ 0 D3 Text GLabel 9100 3550 0 50 Input ~ 0 F4 Text GLabel 9100 3650 0 50 Input ~ 0 E3 Text GLabel 9100 3750 0 50 Input ~ 0 E5 Text GLabel 9100 3850 0 50 Input ~ 0 F5 Text GLabel 9100 3950 0 50 Input ~ 0 A2 Text GLabel 9100 4050 0 50 Input ~ 0 B1 Text GLabel 9100 4150 0 50 Input ~ 0 B2 Text GLabel 9100 4250 0 50 Input ~ 0 C2 Text GLabel 9100 4350 0 50 Input ~ 0 C1 Text GLabel 9100 4450 0 50 Input ~ 0 D1 Text GLabel 9100 4550 0 50 Input ~ 0 D2 Text GLabel 9100 4650 0 50 Input ~ 0 E1 Text GLabel 9100 4750 0 50 Input ~ 0 H4 Text GLabel 9100 4850 0 50 Input ~ 0 G5 Text GLabel 9100 4950 0 50 Input ~ 0 H5 Text GLabel 9100 5050 0 50 Input ~ 0 H3 Text GLabel 9100 5150 0 50 Input ~ 0 G3 Text GLabel 9100 5250 0 50 Input ~ 0 F3 Text GLabel 9100 5350 0 50 Input ~ 0 F2 Text GLabel 9100 5450 0 50 Input ~ 0 E2 $Comp L Lattice_ECP5_FPGA:ECP5U_85_CABGA381 U? U 5 1 615D3ABE P 4900 2250 AR Path="/6255F87B/615D3ABE" Ref="U?" Part="1" AR Path="/629A862A/615D3ABE" Ref="U1" Part="5" F 0 "U1" H 5150 2850 60 0000 L CNN F 1 "ECP5U_85_CABGA381" H 5150 2750 60 0000 L CNN F 2 "Package_BGA:Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD" H 5050 2300 60 0001 R CNN F 3 "" H 5050 2100 60 0001 R CNN F 4 "ECP5U_85" H 5050 2200 60 0001 R CNN "manf#" 5 4900 2250 1 0 0 -1 $EndComp Text GLabel 800 2450 0 50 Input ~ 0 CLKA Text GLabel 800 2250 0 50 Input ~ 0 CLKB Text GLabel 800 3250 0 50 Input ~ 0 PRSNT_L Text GLabel 800 3350 0 50 Input ~ 0 PRSNT_R $EndSCHEMATC