728 lines
18 KiB
Plaintext
728 lines
18 KiB
Plaintext
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EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 4 5
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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Wire Wire Line
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2900 6550 2900 6650
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$Comp
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L power:GND #PWR?
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U 1 1 62B4885D
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P 2400 7450
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AR Path="/62B4885D" Ref="#PWR?" Part="1"
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AR Path="/61CBBC03/62B4885D" Ref="#PWR?" Part="1"
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AR Path="/629A862A/62B4885D" Ref="#PWR0136" Part="1"
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F 0 "#PWR0136" H 2400 7200 50 0001 C CNN
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F 1 "GND" H 2405 7277 50 0000 C CNN
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F 2 "" H 2400 7450 50 0001 C CNN
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F 3 "" H 2400 7450 50 0001 C CNN
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1 2400 7450
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1 0 0 -1
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$EndComp
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Wire Wire Line
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2400 7450 2400 7350
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Wire Wire Line
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2600 7000 2500 7000
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Wire Wire Line
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2500 7000 2500 6650
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Wire Wire Line
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2500 6650 2900 6650
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Connection ~ 2900 6650
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Wire Wire Line
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2900 6650 2900 6700
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$Comp
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L Device:C C?
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U 1 1 62B48869
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P 2200 7000
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AR Path="/62B48869" Ref="C?" Part="1"
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AR Path="/61CBBC03/62B48869" Ref="C?" Part="1"
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AR Path="/629A862A/62B48869" Ref="C31" Part="1"
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F 0 "C31" H 2315 7046 50 0000 L CNN
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F 1 "0.1uF" H 2315 6955 50 0000 L CNN
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F 2 "Capacitor_SMD:C_0603_1608Metric" H 2238 6850 50 0001 C CNN
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F 3 "~" H 2200 7000 50 0001 C CNN
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1 2200 7000
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1 0 0 -1
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$EndComp
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Wire Wire Line
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2500 6650 2200 6650
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Wire Wire Line
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2200 6650 2200 6850
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Connection ~ 2500 6650
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Wire Wire Line
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2200 7150 2200 7350
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Wire Wire Line
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2200 7350 2400 7350
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Text GLabel 4300 7100 2 50 Input ~ 0
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CLKB
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Text Notes 3250 6500 0 118 ~ 0
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System Clock
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Text GLabel 4300 6900 2 50 Input ~ 0
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CLKA
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$Comp
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L ETXO_Osc:ETXO-4Pin U?
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U 1 1 62B48877
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P 2900 7000
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AR Path="/62B48877" Ref="U?" Part="1"
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AR Path="/61CBBC03/62B48877" Ref="U?" Part="1"
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AR Path="/629A862A/62B48877" Ref="U9" Part="1"
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F 0 "U9" H 2700 7250 50 0000 L CNN
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F 1 "ETXO-4Pin" H 2950 7250 50 0000 L CNN
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F 2 "ECP5_BOARD:OSC_ECS-TXO-25CSMV-320-DY-TR" H 2900 7000 50 0001 C CNN
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F 3 "" H 2900 7000 50 0001 C CNN
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1 2900 7000
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1 0 0 -1
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$EndComp
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Wire Wire Line
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2900 7300 2900 7350
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Wire Wire Line
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2900 7350 2400 7350
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Connection ~ 2400 7350
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Text Notes 3100 7600 0 50 ~ 0
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Connect both jumpers to use onboard\nXO instead of external clock
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$Comp
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L Device:Jumper JP?
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U 1 1 62B4888D
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P 3800 6900
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AR Path="/61CBBC03/62B4888D" Ref="JP?" Part="1"
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AR Path="/629A862A/62B4888D" Ref="JP2" Part="1"
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F 0 "JP2" V 3750 7150 50 0000 R CNN
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F 1 "Jumper" V 3900 7250 50 0000 R CNN
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F 2 "Connector_PinHeader_1.27mm:PinHeader_1x02_P1.27mm_Vertical" H 3800 6900 50 0001 C CNN
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F 3 "~" H 3800 6900 50 0001 C CNN
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1 3800 6900
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-1 0 0 -1
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$EndComp
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$Comp
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L Device:Jumper JP?
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U 1 1 62B48896
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P 3800 7100
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AR Path="/61CBBC03/62B48896" Ref="JP?" Part="1"
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AR Path="/629A862A/62B48896" Ref="JP3" Part="1"
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F 0 "JP3" V 3750 7350 50 0000 R CNN
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F 1 "Jumper" V 3900 7450 50 0000 R CNN
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F 2 "Connector_PinHeader_1.27mm:PinHeader_1x02_P1.27mm_Vertical" H 3800 7100 50 0001 C CNN
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F 3 "~" H 3800 7100 50 0001 C CNN
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1 3800 7100
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-1 0 0 1
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$EndComp
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$Comp
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L power:VBUS #PWR0138
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U 1 1 62B4C07B
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P 2900 6550
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F 0 "#PWR0138" H 2900 6400 50 0001 C CNN
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F 1 "VBUS" H 2915 6723 50 0000 C CNN
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F 2 "" H 2900 6550 50 0001 C CNN
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F 3 "" H 2900 6550 50 0001 C CNN
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1 2900 6550
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1 0 0 -1
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$EndComp
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$Comp
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L power:VBUS #PWR0139
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U 1 1 62B7CF62
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P 5300 6750
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F 0 "#PWR0139" H 5300 6600 50 0001 C CNN
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F 1 "VBUS" H 5315 6923 50 0000 C CNN
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F 2 "" H 5300 6750 50 0001 C CNN
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F 3 "" H 5300 6750 50 0001 C CNN
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1 5300 6750
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1 0 0 -1
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$EndComp
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$Comp
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L power:+1V8 #PWR0140
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U 1 1 62B7E6D5
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P 5900 6750
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F 0 "#PWR0140" H 5900 6600 50 0001 C CNN
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F 1 "+1V8" H 5915 6923 50 0000 C CNN
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F 2 "" H 5900 6750 50 0001 C CNN
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F 3 "" H 5900 6750 50 0001 C CNN
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1 5900 6750
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1 0 0 -1
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$EndComp
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$Comp
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L Device:Jumper JP?
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U 1 1 62B7F21D
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P 5600 7000
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AR Path="/61CBBC03/62B7F21D" Ref="JP?" Part="1"
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AR Path="/629A862A/62B7F21D" Ref="JP1" Part="1"
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F 0 "JP1" V 5550 7250 50 0000 R CNN
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F 1 "Jumper" V 5700 7350 50 0000 R CNN
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F 2 "Connector_PinHeader_1.27mm:PinHeader_1x02_P1.27mm_Vertical" H 5600 7000 50 0001 C CNN
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F 3 "~" H 5600 7000 50 0001 C CNN
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1 5600 7000
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1 0 0 -1
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$EndComp
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Wire Wire Line
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5900 6750 5900 7000
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Wire Wire Line
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5300 7000 5300 6750
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Text Notes 4850 7450 0 50 ~ 0
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Connect jumper to use onboard 1.8V\nas VBUS for I/O and clock (incl. onboard osc.)
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Text GLabel 1150 7050 0 50 Input ~ 0
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ID0
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Text GLabel 1150 7150 0 50 Input ~ 0
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ID1
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$Comp
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L Device:R_US R?
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U 1 1 62BBA733
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P 1250 6800
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AR Path="/62BBA733" Ref="R?" Part="1"
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AR Path="/61CBBC03/62BBA733" Ref="R?" Part="1"
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AR Path="/629A862A/62BBA733" Ref="R13" Part="1"
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F 0 "R13" H 1182 6754 50 0000 R CNN
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F 1 "4.7k" H 1182 6845 50 0000 R CNN
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F 2 "Resistor_SMD:R_0603_1608Metric" V 1290 6790 50 0001 C CNN
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F 3 "~" H 1250 6800 50 0001 C CNN
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1 1250 6800
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1 0 0 1
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$EndComp
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$Comp
|
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L Device:R_US R?
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U 1 1 62BBA73F
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P 1450 6800
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AR Path="/62BBA73F" Ref="R?" Part="1"
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AR Path="/61CBBC03/62BBA73F" Ref="R?" Part="1"
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AR Path="/629A862A/62BBA73F" Ref="R14" Part="1"
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F 0 "R14" H 1518 6846 50 0000 L CNN
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F 1 "4.7k" H 1518 6755 50 0000 L CNN
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F 2 "Resistor_SMD:R_0603_1608Metric" V 1490 6790 50 0001 C CNN
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F 3 "~" H 1450 6800 50 0001 C CNN
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1 1450 6800
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1 0 0 -1
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||
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$EndComp
|
||
|
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Wire Wire Line
|
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|
|
1250 6950 1250 7050
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Wire Wire Line
|
||
|
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1250 7050 1150 7050
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||
|
|
Wire Wire Line
|
||
|
|
1450 6950 1450 7150
|
||
|
|
Wire Wire Line
|
||
|
|
1450 7150 1150 7150
|
||
|
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Wire Wire Line
|
||
|
|
1250 6650 1250 6600
|
||
|
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Wire Wire Line
|
||
|
|
1250 6600 1350 6600
|
||
|
|
Wire Wire Line
|
||
|
|
1350 6600 1350 6550
|
||
|
|
Wire Wire Line
|
||
|
|
1350 6600 1450 6600
|
||
|
|
Wire Wire Line
|
||
|
|
1450 6600 1450 6650
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||
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Connection ~ 1350 6600
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||
|
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Text Notes 700 7350 0 118 ~ 0
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|
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Core ID pullup
|
||
|
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Text Notes 950 7550 0 50 ~ 0
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Defaults core ID\nto 3 (standalone)
|
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$Comp
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||
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L power:VBUS #PWR0141
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U 1 1 62BBE019
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P 1350 6550
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F 0 "#PWR0141" H 1350 6400 50 0001 C CNN
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F 1 "VBUS" H 1365 6723 50 0000 C CNN
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F 2 "" H 1350 6550 50 0001 C CNN
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F 3 "" H 1350 6550 50 0001 C CNN
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1 1350 6550
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1 0 0 -1
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$EndComp
|
||
|
|
Text GLabel 800 2850 0 50 Input ~ 0
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|
|
UP_L
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Text GLabel 800 2950 0 50 Input ~ 0
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UP_R
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|
|
Text GLabel 800 2750 0 50 Input ~ 0
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ID1
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Text GLabel 800 2650 0 50 Input ~ 0
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ID0
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Text GLabel 800 3050 0 50 Input ~ 0
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SC_L
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Text GLabel 800 3150 0 50 Input ~ 0
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SC_R
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$Comp
|
||
|
|
L power:VBUS #PWR0142
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U 1 1 62CA27EF
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|
P 2300 1250
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||
|
|
F 0 "#PWR0142" H 2300 1100 50 0001 C CNN
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||
|
|
F 1 "VBUS" H 2315 1423 50 0000 C CNN
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||
|
|
F 2 "" H 2300 1250 50 0001 C CNN
|
||
|
|
F 3 "" H 2300 1250 50 0001 C CNN
|
||
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1 2300 1250
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||
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1 0 0 -1
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||
|
|
$EndComp
|
||
|
|
Wire Wire Line
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||
|
|
2300 1250 2300 1350
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||
|
|
Text Notes 4700 7250 0 118 ~ 0
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|
|
Optional Onboard VBUS
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||
|
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Text Notes 7150 6900 0 118 ~ 0
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||
|
|
I/O and Clock
|
||
|
|
Wire Wire Line
|
||
|
|
3200 7000 3400 7000
|
||
|
|
Wire Wire Line
|
||
|
|
3400 7000 3400 6900
|
||
|
|
Wire Wire Line
|
||
|
|
3400 6900 3500 6900
|
||
|
|
Wire Wire Line
|
||
|
|
3400 7000 3400 7100
|
||
|
|
Wire Wire Line
|
||
|
|
3400 7100 3500 7100
|
||
|
|
Connection ~ 3400 7000
|
||
|
|
Wire Wire Line
|
||
|
|
4300 6900 4100 6900
|
||
|
|
Wire Wire Line
|
||
|
|
4100 7100 4300 7100
|
||
|
|
$Comp
|
||
|
|
L power:VBUS #PWR01
|
||
|
|
U 1 1 61760C08
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||
|
|
P 4550 1150
|
||
|
|
F 0 "#PWR01" H 4550 1000 50 0001 C CNN
|
||
|
|
F 1 "VBUS" H 4565 1323 50 0000 C CNN
|
||
|
|
F 2 "" H 4550 1150 50 0001 C CNN
|
||
|
|
F 3 "" H 4550 1150 50 0001 C CNN
|
||
|
|
1 4550 1150
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||
|
|
1 0 0 -1
|
||
|
|
$EndComp
|
||
|
|
Wire Wire Line
|
||
|
|
4550 1150 4550 1250
|
||
|
|
$Comp
|
||
|
|
L power:VBUS #PWR02
|
||
|
|
U 1 1 617631B1
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||
|
|
P 6700 1250
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||
|
|
F 0 "#PWR02" H 6700 1100 50 0001 C CNN
|
||
|
|
F 1 "VBUS" H 6715 1423 50 0000 C CNN
|
||
|
|
F 2 "" H 6700 1250 50 0001 C CNN
|
||
|
|
F 3 "" H 6700 1250 50 0001 C CNN
|
||
|
|
1 6700 1250
|
||
|
|
1 0 0 -1
|
||
|
|
$EndComp
|
||
|
|
Wire Wire Line
|
||
|
|
6700 1250 6700 1350
|
||
|
|
$Comp
|
||
|
|
L power:VBUS #PWR03
|
||
|
|
U 1 1 617657B4
|
||
|
|
P 8800 1250
|
||
|
|
F 0 "#PWR03" H 8800 1100 50 0001 C CNN
|
||
|
|
F 1 "VBUS" H 8815 1423 50 0000 C CNN
|
||
|
|
F 2 "" H 8800 1250 50 0001 C CNN
|
||
|
|
F 3 "" H 8800 1250 50 0001 C CNN
|
||
|
|
1 8800 1250
|
||
|
|
1 0 0 -1
|
||
|
|
$EndComp
|
||
|
|
Wire Wire Line
|
||
|
|
8800 1250 8800 1350
|
||
|
|
$Comp
|
||
|
|
L power:VBUS #PWR04
|
||
|
|
U 1 1 61775788
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||
|
|
P 11000 1350
|
||
|
|
F 0 "#PWR04" H 11000 1200 50 0001 C CNN
|
||
|
|
F 1 "VBUS" H 11015 1523 50 0000 C CNN
|
||
|
|
F 2 "" H 11000 1350 50 0001 C CNN
|
||
|
|
F 3 "" H 11000 1350 50 0001 C CNN
|
||
|
|
1 11000 1350
|
||
|
|
1 0 0 -1
|
||
|
|
$EndComp
|
||
|
|
Wire Wire Line
|
||
|
|
11000 1350 11000 1450
|
||
|
|
Text Notes 9550 5800 0 118 ~ 0
|
||
|
|
GPIO Bank 5
|
||
|
|
Text Notes 7500 5800 0 118 ~ 0
|
||
|
|
GPIO Bank 4
|
||
|
|
Text Notes 1100 5800 0 118 ~ 0
|
||
|
|
GPIO Bank 1
|
||
|
|
Text Notes 3150 5800 0 118 ~ 0
|
||
|
|
GPIO Bank 2
|
||
|
|
Text Notes 5350 5800 0 118 ~ 0
|
||
|
|
GPIO Bank 3
|
||
|
|
$Comp
|
||
|
|
L Lattice_ECP5_FPGA:ECP5U_85_CABGA381 U?
|
||
|
|
U 7 1 615DFD6A
|
||
|
|
P 9100 2350
|
||
|
|
AR Path="/6255F87B/615DFD6A" Ref="U?" Part="1"
|
||
|
|
AR Path="/629A862A/615DFD6A" Ref="U1" Part="7"
|
||
|
|
F 0 "U1" H 9350 2950 60 0000 L CNN
|
||
|
|
F 1 "ECP5U_85_CABGA381" H 9350 2850 60 0000 L CNN
|
||
|
|
F 2 "Package_BGA:Lattice_caBGA-381_17.0x17.0mm_Layout20x20_P0.8mm_Ball0.4mm_Pad0.4mm_NSMD" H 9250 2400 60 0001 R CNN
|
||
|
|
F 3 "" H 9250 2200 60 0001 R CNN
|
||
|
|
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|
|
5 4900 2250
|
||
|
|
1 0 0 -1
|
||
|
|
$EndComp
|
||
|
|
Text GLabel 800 2450 0 50 Input ~ 0
|
||
|
|
CLKA
|
||
|
|
Text GLabel 800 2250 0 50 Input ~ 0
|
||
|
|
CLKB
|
||
|
|
Text GLabel 800 3250 0 50 Input ~ 0
|
||
|
|
PRSNT_L
|
||
|
|
Text GLabel 800 3350 0 50 Input ~ 0
|
||
|
|
PRSNT_R
|
||
|
|
$EndSCHEMATC
|